1. Field
The field relates to a flat panel display device and a method of fabricating the same, and more particularly, to a flat panel display device including a capacitor having first and second capacitors, wherein the capacitor has a first capacitor electrode and a third capacitor electrode which are different in area.
2. Description of Related Technology
Generally, an organic light emitting diode (OLED) display device, one kind of a flat panel display device, is a self-emissive display device which electrically excites an emissive organic compound so as to emit light, and is classified as a passive-matrix device or an active-matrix device based on its driving mechanism.
The active-matrix OLED display device includes a thin film transistor, and is suitable for large-sized display device because of less power consumption than the passive-matrix OLED display device.
This active-matrix OLED display device includes thin film transistors and capacitors in a compensation circuit.
FIG. 1 is a cross-sectional view of a conventional OLED display device.
Referring to FIG. 1, an amorphous silicon layer is formed on a substrate 10 including a first region a in which an organic light emitting diode (OLED) and a thin film transistor are formed and a second region b in which a capacitor is formed, and then crystallized to form a polycrystalline silicon layer.
After crystallization into the polycrystalline silicon layer, the polycrystalline silicon layer is patterned so as to form a semiconductor layer 11 in the first region a, and form a first capacitor electrode 31 in the second region b.
Then, a gate insulating layer 12 is formed on the entire surface of the substrate, and a gate metal layer is deposited on the gate insulating layer 12. The gate metal layer is patterned so as to form a gate electrode 13 corresponding to a certain region of the semiconductor layer 11 in the first region a.
The gate metal layer is patterned so as to form a second capacitor electrode 32 corresponding to a certain region of the first capacitor electrode 31 on the gate insulating layer 12 in the second region b, while forming the gate electrode 13.
Subsequently, n- or p-type impurity ions are injected into the semiconductor layer 11, thereby forming source and drain regions 11a and 11b. Here, a channel region 11c is formed between the source and drain regions 11a and 11b of the semiconductor layer 11.
After forming an interlayer insulating layer 14 on the entire surface of the substrate, the interlayer insulating layer 14 and the gate insulating layer 12 are etched in the first region a, thereby forming first and second contact holes 15a and 15b which partially expose the source and drain regions 11a and 11b of the semiconductor layer 11, respectively.
A third contact hole 40a partially exposing the second capacitor electrode 32 and a fourth contact hole 33a partially exposing the first capacitor electrode 31 are formed in the second regions b.
Then, source and drain metal layers are deposited on the interlayer insulating layer 14 and are then patterned in a certain shape in the first region a so as to form source and drain electrodes 15 which are connected with the source and drain regions 11a and 11b of the semiconductor layer 11 through the first and second contact holes 15a and 15b, respectively.
Also, a first power voltage line 40 connected with the second capacitor electrode 32 through a third contact hole 40a, and a third capacitor electrode 33 connected with the first capacitor electrode 31 through a fourth contact hole 33b are formed in the second region b.
The first capacitor electrode 31 and the second capacitor electrode 32 constitute a first capacitor. Here, the first capacitor electrode 31 is a lower electrode of the first capacitor, and the second capacitor electrode 32 is an upper electrode of the first capacitor. Also, the second capacitor electrode 32 and the third capacitor electrode 33 constitute a second capacitor, wherein the second capacitor electrode 32 is a lower electrode of the second capacitor, and the third capacitor electrode 33 is an upper electrode of the second capacitor.
Here, the first capacitor electrode 31 and the third capacitor electrode 33 have the same area so that an area S2 corresponding to the third capacitor electrode 33 overlap of the second capacitor electrode 32 is equal to an area S1 corresponding to the second capacitor electrode 32 overlap of the first capacitor electrode 31.
Thus, when the permittivity and distance between the first capacitor and the second capacitor are equal, the capacitances of the capacitors are also equal.
A passivation layer 16 is formed on the entire surface of the substrate, and a planarization layer (not illustrated) may be formed of an organic material to reduce a step height on the substrate.
Here, a pixel electrode 17 is formed in the first region a, which is electrically connected with one of the source and drain electrodes 15 through a via hole passing through the passivation layer 16 or the planarization layer.
Subsequently, a pixel defining layer 18 including an opening partially exposing the pixel electrode 17 is formed. An organic layer 19 including an organic emitting layer is formed on the pixel electrode 17 exposed by the opening, and a counter electrode 20 is formed on the entire surface of the substrate, and thus the OLED display device may be completed.
However, the distance between the third capacitor electrode 33 and the first power voltage line 40 is relatively small, which is within 5 μm, because the area of the third capacitor electrode 33 has to be large to increase the capacitance of the capacitor.
The small distance between interconnections may cause a short circuit between the third capacitor electrode 33 and the first power voltage line 40 in the patterning process.
As a result, the capacitor is short-circuited, so that the voltage between the gate and the source electrode of the thin film transistor is 0 and no current flows, and thus a dark spot occurs in the OLED display device.